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APPLICATION NOTE
TEA2037A HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
By B. D'HALLUIN
SUMMARY
I II II.1 II.1.1 II.1.2 II.1.3 II.2 II.2.1 II.2.2 II.2.3 II.3 II.4 II.5 II.5.1 II.5.2 II.5.3 II.6 II.7 II.8 II.9 II.10 III III.1 III.1.1 III.1.2 III.1.3 III.2 III.3 III.4 III.5 III.6 III.7 IV IV.1 IV.2 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION OF TEA2037A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNC. PULSE SEPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extraction of Sync. Pulses from the Composite Video Signal . . . . . . . . . . . . . . . . . . . . . Negative TTL Sync. (monitor application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Sync Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LINE OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LINE OUTPUT STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHASE COMPARATOR (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FRAME OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FRAME OUTPUT AMPLIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FRAME FLYBACK GENERATOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHUNT REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THERMAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MONITOR APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-cost Monitor (French Minitel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor with Geometry and Frequency Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . High Frequency Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLACK & WHITE APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USING COMPOSITE TTL SYNCHRONIZATION SIGNALS. . . . . . . . . . . . . . . . . . . . . . DIRECT FRAME SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONSTANT AMPLITUDE 50/60Hz SWITCHING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODIFYING THE LINE OUTPUT DURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTING THE TEA2037A FROM +6V POWER SUPPLY. . . . . . . . . . . . . . . . . . . . . . DESIGN CONSIDERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRECAUTION FOR INTERLACED SCANNING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRINTED CIRCUIT BOARD LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
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1/17
AN410/1293
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
I - INTRODUCTION The TEA2037A is a horizontal and vertical deflection circuit for monitors and black and white TV sets. This device includes all functions required for deflection, namely : - Line and frame sync separation - Line oscillator with phase comparator - Driver stage for line deflection darlington transistor - Frame oscillator - Frame amplifier with flyback generator for direct drive of the vertical deflection yoke. The TEA2037A is particularly well-suited for lowcost monitors since it is cased in a low-cost package and requires a few number of external components and hence optimized for small displays. However, application areas are by no means limited. Sophisticated applications requiring various adjustment possibilities such as for display geometry and centering settings (amplitude, linearity,...) and operating at different line and frame frequencies (line frequencies up to 64kHz), are readily configured around TEA2037A. In large screen applications, addition of a heatsink mounted on TEA2037A will enable the vertical deflection yoke current to be boosted to 2A peakto-peak. II.1.1 - Block Diagram Figure 1 II - FUNCTIONAL DESCRIPTION OF TEA2037A II.1 - General Description The TEA2037A is a 16-pin DIP package. The 4 center pins (2 on each side) are connectedtogether and used as heatsink. From composite video or TTL-compatible sync. signals, the device will extract and generate all signals required for the line scanning darlington transistor and direct drive of the frame yoke. The following functional blocks are implemented on-chip : - Line and frame sync. separator - Line oscillator - Line phase comparator - Line output stage - Frame oscillator - Frame amplifier - Frame flyback generator - Shunt regulator The common device power supply is implemented by the on-chip shunt regulator. In order to optimize the drive to frame deflection yoke and also enable appropriate use of the flyback generator, the frame amplifier is powered by an independentsupply. The ground is connected to the 4 center pins of the device.
16
1
7
+
POWER STAGE
3
2
4
FRAME OSCILLATOR FRAME-SYNC. OSCILLATOR SEPARATOR
FRAME
FLYBACK GENERATOR
5 12 13
8 6
Yoke
15
INPUT STAGE
PHASE DETECTOR
LINE OSCILLATOR
OUTPUT STAGE
14
TEA2037A
11 10 9 VCC1
2037A-02.EPS
2/17
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
II.1.2 - Pin Description
1 2 3 4, 5 6 7 8 9 10 11 14 15 16 Frame Oscillator VCC2 (Flyback generator power supply) Flyback Generator Output Ground Frame Feed-back (frame amplifier inverting input) VCC2 (positive power supply for frame output stage) Frame Output (direct drive to frame yoke) Line Oscillator Phase Comparator Output Phase Comparator Input (line flyback) Line Output (drive to line darlington transistor) Video Input (or TTL-compatible sync.) VCC1 (shunt regulator)
Figure 3
VIDEO LEVEL
0 1 line (64s)
t
PIN 15 VOLTAGE (V)
0
t
II.1.3 - Package
Batwing DIP16 (plastic package)
- The sync. detection level is set at 1.6V. - The value of R2 is typically 1M (fixed for a good internal bias). - Resistor R1 limits the output current of Pin 15. As illustrated in the Figure 4, it is recommended to employ a low-pass filter which will suppress highfrequency harmonics susceptible to produce jitters on line sync signal in composite video TV applications. Figure 4
TEA2037A
II.2.1 - Extraction of Sync. Pulses from the Composite Video Signal (TV application) Figure 2 : Synchronization Separator Circuit II.2.2 - Negative TTL Sync. (Monitor application) Figure 5
VR
SL1 SL2 VR 15
TTL Sync
TEA2037A
2037A-14.EPS
15
R1 Video
2037A-03.EPS
R2
In monitor application, the sync. signal is generally separated from the video signal. In this case, the sync. signal is applied to Pin 15 through a single limiting resistor. Similar to the former case, the sync. is detected when the input voltage falls below 1.6V level.
3/17
2037A-13.EPS
II.2 - Sync. Pulse Separator The TEA2037A extracts, first the line and frame sync. pulses from the composite video signal and then the largest pulses, i.e., the frame syncs.
1.5k Composite Video 220pF
100nF
15
1M
2037A-12.EPS
1.6
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
Figure 6
TTL SYNC LEVEL (V)
II.3 - Line Oscillator Figure 9
5
R VCC1 C
1.6 t
16
9
PIN 15 VOLTAGE (V)
5
2037A-15.EPS
1.4k
1.6 t
II.2.3 - Frame Sync. Extraction Figure 7 : Frame Separator
VZ Q3
TEA2037A
Figure 10
Q4
PIN 9 VOLTAGE(V)
I
ST1 VZ / 2
ST2
6.6 3.2 t Line Period
2037A-04.EPS
SL1
This function is processed internally and hence does not require any external component. Line and frame sync. pulses are distinguished by an integrated capacitor which is more or less discharged during each sync. pulse interval as follows : - if the sync pulse duration is short, i.e. it is line sync, then the capacitor is slightly discharged - on the other hand, if the pulse width is larger, the capacitor is fully discharged and an internal frame signal is thus generated. Figure 8
SYNC PULSE
t INTEGRATED CAPACITOR VOLTAGE (V)
VZ VZ /2 t
2037A-16.EPS
This function is processed internally and hence does not require any external component. Line and frame sync. pulses are distinguished by an integrated capacitor which is more or less discharged during each sync. pulse interval as follows : - if the sync pulse duration is short, i.e. it is line sync, then the capacitor is slightly discharged - on the other hand, if the pulse width is larger, the capacitor is fully discharged and an internal frame signal is thus generated. The line saw-tooth is generated by charging an external capacitor on Pin 9 via a resistor connected to VCC1 (Pin 16). The capacitor is discharged via an internal 1.4k resistor. The saw-tooth amplitude is set by two on-chip threshold levels : - lower threshold : 3.2V - higher threshold : 6.6V The free-running period is approximately given by the following relationship :
TOSC 0.85 RC
4/17
2037A-18.EPS
3I
2037A-17.EPS
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
The phase comparator will modify the capacitor charge by injecting a positive or negative current so as to produce correct phase and frequency relationships with respect to the synchronization signal. II.4 - Line Output Stage The line output stage has been designed for direct Figure 11
VCC
base drive of the horizontal scanning darlington transistor. The low level interval on Pin 14, i.e. the power line transistor blocking period, is determined by the time when the voltage of the line oscillator capacitor (Pin 9) is below 4.8V (internally set threshold level). In a typical application, this interval corresponds to 22s at 64s free-running period.
TEA2037A
R1 6.6V 3.2V Line Sawtooth 14 R2 D R3 VREF = 4.8V
2037A-19.EPS
C T LINE YOKE
T1 = 470 R2 = 10 R3 = 47
C = 2.2F D : 1N4148 T : BU184
Figure 12
DARLINGTON PIN14 PIN9 VOLTAGE (V) VOLTAGE (V) VCE
6.6 4.8 3.2 t
22s 64s
II.5 - Phase Comparator (PLL) II.5.1 - Functional Description The duty of phase comparator is to synchronize the horizontal scanning with the line sync pulse and ensure correct line flyback during the horizontal blanking phase. Figure 13
VIDEO SIGNAL
V(sat)
t
LINE FLYBACK
2037A-21.EPS
t
t
2037A-20.EPS
The line flyback signal (i.e. the pulse on the collector of the line scanning transistor) is compared with the line sync. signal issued by sync. separator. If the detected coincidence is incorrect, the comparator will then generate an appropriate positive or negative current so as to charge or discharge the line oscillator capacitor thereby providing for frequency and phase locking.
YOKE CURRENT
5/17
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
II.5.2 - Phase Comparator Operation Figure 14
V CC1
T3 I3 I1 T1
T4
The line flyback signal goes through integrator network R1C1 the output of which, a saw-tooth signal, is applied to comparator input (Pin 11) via capacitor C2. The comparator input stage is formed by the differential pair T1 and T2. T3 and T4 transistors are arranged in current mirror configuration and thus : i3 = i2
I2 T2 VREF
The sum of currents going through T1 and T2 transistors is determined by the current generator "I" so that : I = i 1+ i2
I LS T5 FS T6
I OUT
The comparator output current is the difference current through the differential pair, i.e. :
Line Oscillator 10 R3 R4 9 R5
2037A-22.EPS
11 C2 C1 R1 C3 C4
iOUT = i2 - i1 The comparator is enabled by T5 transistor only during the line sync. interval. Transistor T6 inhibits the phase comparison during the frame sync. interval. During the first portion of the flyback, the voltage at comparator input (Pin 11) is lower than the reference voltage. T1 is off and T2 conducts ; consequently the comparator output goes positive : iOUT = + I During the second portion, the input voltage exceeds the reference voltage and as a result, the comparator ouput falls to negative level :
VC
C5
V CC1
Figure 15 : Phase Comparator
Line Flyback
Integrated Flyback
iOUT = - I If the line flyback is in retard with respect to the horizontal sync. pulse (which is the case of too long line periods), the interval for which the phase comparator's output current is positive would increase. This current is then filtered and applied to the line oscillator capacitor (C5) thereby accelerating its charge-up phase and hence reducing the line period. Inverse action takes place if the line flyback is in advance - the negative current at comparator's output will rise, C5 is charged more slowly and the line period is thus increased.
Sync Pulse
Output Current
2037A-06.EPS
6/17
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
Figure 16
LINE FLYBACK
VREF
SAWTOOTH (Pin 11)
VREF
INTERNAL LINE SYNC PULSE
OUTPUT CURRENT (Pin 10)
2037A-23.EPS
The line flyback in retard with respect to the line sync pulse
The line flyback in advance with respect to the line sync pulse
II.5.3 - Output Filter Figure 17
10 9
R3
R4
R5
C3
C4
C5
VCC1
FILTER
Figure 18
f1
f2 FREQUENCY
f3
f1 = f2 =
1 2 (R3 + R4) C3 f3 = R3 + R4 2R3R4C4
1 2R3C3
The duty of the output filter is to ensure the stability of the locked loop and its characteristics will have a partial influence on capture range and also on capture time. The holding range, which is larger than the capture range, dependson the ratio of the current available at the comparator output and the charging current of the line oscillator. The holding range does not depend directly on the cut-off frequencies of the output filter. But, as the voltage range at the comparator output is limited, a too high value for R4 will limit the holding range. The sync. pulse duration has significant influence on capture range and also on the holding range of the device. The output current duration is directly related to synchronization pulse width. - First the R5 x C5 product is selected to yield the required free-running line oscillator frequency. - Then, the value of C5 capacitor is selected as follows : * for monitor applications (large holding range) low value; e.g. : 2.2nF @ 16kHz, 1nF @ 32kHz * for TV applications * higher value; e.g. : 4.7nF @ 16kHz - Finally, the filter components are selected to match the required capture range. (R4 100k to prevent comparator output saturation)
7/17
GAIN
2037A-25.EPS
2037A-24.EPS
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
II.6 - Frame Oscillator Similar to line oscillator, the frame saw-tooth is generated by charging an external capacitor on Pin 1 through a resistor connected to VCC1. Figure 19
R VCC1 16 9 C
The free-running period is approximately given by : TOSC 0.15 RC Synchronization is achieved by period reduction. The frame sync. pulse issued by the sync. separator will modify the current through the resistor bridge which is used to set the saw-tooth threshold levels. The minimum synchronized frame period (MSFP) is given by :
MSFP TOSC
TEA2037A
500
1.8
Figure 20
PIN 1 VOLTAGE (V) Amplitude
3.1 2 Frame Free-running period
2037A-26.EPS
Frame Sync Pulse
II.7 - Frame Output Amplifier The frame saw-tooth generated by frame oscillator is first inverted (Gain : - 0.4) and then applied to the non-inverting input of the frame amplifier. The output current capability of this amplifier is as high as 1Athus enabling to drive vertical deflection yokes requiring 2A peak-to-peak. As a function of dissipated power, the device may require the addition of a heatsink. A feed-back loop is connected to the inverting input of the frame amplifier (Pin 6). As the CRT screen is not part of a sphere centered on the deflectioncenter point, if the yoke is actually driven by a saw-tooth waveform, the image is expanded at the top and bottom. The yoke must therefore be provided with an "S" waveform current, by applying linearity correction. Figure 21
VCC2
7
t Amplitude
INTERNAL PIN 1 FRAME SYNC VOLTAGE (V)
3.1 2 t
Frame Sawtooth
8
R3
6
R6
FRAME YOKE
5
4
12
13
C3
2037A-27.EPS
R4 R5
Sync Period
C2
R2
C1
t
P
R1
2037A-28.EPS
The capacitor is discharged via an internal 500 resistor. The saw-tooth amplitude is set at two on-chip threshold levels.
8/17
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
Figure 22
FRAME SAWTOOTH (non-inverting input)
The configuration of the flyback generator is depicted in Figure 23. Figure 23
D1
t
C
D2
VCC
2 7 3
OUTPUT VOLTAGE (Pin 8)
K
t
YOKE CURRENT
T1
2037A-29.EPS
t
T2
AMPLIFIER SUPPLY VCC2
The circuit configuration depicted above does not require any linearity adjustment - only an amplitude adjustment potentiometer "P" has been provided for. - D.C. Feedback : The C1 capacitor is charged to approximately 1/2 x VCC2. Divider bridge formed by R2 + R4 and R5 networks will set the d.c. feedback. The component values of this divider network will be choosen to avoid saturation at top and bottom of the output voltage (Pin 6 biasing voltage is approximately 0.6V). - Linearity Correction : Aparabolic signal at frame frequency is available on "+" terminal of the C1 capacitor. This signal is integrated by R2, C2 network. An "S" waveform is thus obtained,which is applied to Pin 6 via resistor R4. Any correction to this "S" waveform depends on C1 and C2 values. The linearity correction depends on ratio : R2/R4 - Vertical Amplitude : Frame current amplitude is determined by the value of measurement resistor "R1", potentiometer "P" settings and the value of "R5" resistor. II.8 - Frame Flyback Generator The output stage of the vertical amplifier includes a frame flyback generator connected to pin 3. During the vertical scanning flyback time, the value of the yoke inductance "L" must be taken into account since the time constant L/R is no longer negligible. In television applications, the frame blanking time is 1.6ms. Thus when L/R > 1.6 x 10-3, it is necessary to increase the supply voltage to the frame output amplifier so as to reduce the flyback time. This surplus is required only for the frame flyback and energy is wasted by boosting the supply to the amplifier at all times (during the frame scanningtime, the minimum voltage issubstantially RI, where I is peak-to-peak frame current).
During the second half of the vertical scanning time, transistor T2 conducts and capacitor C is charged to VCC through D1, D2, R3 and T2. (Switch K open) On flyback, switch K closes and Pin 3 is connected to VCC. The voltage at Pin 7 (VCC2), which was equal to VCC - VD1, is almost doubled during the flyback time. The only external components required are therefore D1, D2 and C. In addition to reducing the flyback time, the flyback generator reduces the power consumed by the power stage, and can in certain cases avoid the need to use a heatsink. Figure 24
VCC t
AMPLIFIER OUTPUT OUTPUT CURRENT (Yoke Current) VOLTAGE (Pin 8)
t
t
Diode D2 is a low-signal diode (1N4148) but diode D1 must be appropriately rated since the positive current in the first part of the saw-tooth is supplied to the yoke through D1 and T1. A 1N4001 is generally used.
9/17
2037A-31.EPS
2037A-30.EPS
Frame Amplifier Output
8
L, R
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
II.9 - The shunt regulator The TEA2037A incorporates an internal shunt regulator which delivers the common supply voltage VCC to various blocks such as oscillators, comparator, sync separator and so on. The voltage on Pin 16 is 9.7V (9V min, 10.5V max). The value of the series resistor R must be so calculated to obtain a 15mA current on Pin 16 - this current can be 10mA min. and 20mA max. Figure 25
R VCC VCC1
Where : - Ipp = peak-to-peak current through the vertical deflection yoke. - I2 = Pin 7 quiescent current. - VCC2 = Pin 7 voltage. * Power dissipated in deflection yoke and the measurement resistor :
PY = (R Y + RM) I pp 12
2
Where : - Ry = Frame deflection yoke resistance - RM = Measurement resistor value Thus, the overall power dissipated in the integrated circuit is :
16
PD = P1 + P2 - PY I2pp Ipp + I2 - (RY + RM) PD = VCC1I1 + VCC2 12 8
TEA2037A
2037A-32.EPS
The external current supply from VCC1 to both oscillators (i.e. line and frame) can be neglected in majority of cases. The resistor value is found to be 1.2k a t VCC = +28V. At VCC = + 12V, and taking into account the voltage tolerance on Pin 16, a 150 series resistor must be used. II.10 - Thermal Considerations In order to ensure reliable device operation, the dissipated power should be accurately determined. Calculation will allow an evaluation of the dissipated power and should be completed by package temperature measurements in actual applications. According to results obtained, a heatsink may or may not be required. * Power drawn from VCC1 supply :
P1 = VCC1 . I1
In application using the flyback generator, the VCC2 specified above becomes "VCC2 - VD", where VD is the voltage drop across the series diode. Figure 26
VCC2 VCC 16 I1 7 8 Frame Yoke Ly, Ry
2037A-33.EPS 2037A-34.EPS
I2
TEA2037A
13 12 5 4
RM
Figure 27
FRAME YOKE CURRENT
Where I1 is the current through the shunt regulator (Pin 16). * Power drawn from VCC2 supply :
IPP P2 = VCC2 + I2 8
I PP
10/17
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
III - APPLICATIONS III.1 - Monitor Applications III.1.1 - Low-cost monitor (French Minitel Type) (see Figure 28) CHARACTERISTICS - Screen : 9" Monochrome - Frame deflection yoke : 72mH, 40, 220mA peak-to-peak - VCC = + 25V without flyback generator - Frame flyback time : 1.2ms - Vertical frequency : 50Hz (20ms) - Vertical free-running period : 24.5ms - Horizontal frequency : 15 625Hz - Capture range : 5s - Holding range : 10s - Input signal : composite video - Dissipated power : 1.15W - Only one adjustment : vertical amplitude This is a low-cost application used in French Minitel type configurations and requires minimum number of additional components and adjustments. The input is a composite video signal at line freFigure 28
VCC +25V 1k 100F VCC1 910k 5% 180nF 5% 1 15 Line Flyback 15k 22nF 11 47nF 10 100k 22nF 3.9k 2.2nF 2% 35.7k 1% 10 VCC 9 4 5 12 13 14 56k 100 Vertical Amplitude Adjust 16 2 7 3 8 Frame Yoke 72mH, 40 470k 6 220nF 470F 470k 1k 4.7k 100nF
quency = 15 625Hz and frame frequency of 50Hz. The free-running horizontal frequency is determined by the component values of RC network on Pin 9. Since no adjustment is available, precision components must be used to ensure correct synchronization :
[R = 35.7k, 1% and C = 2.2nF, 2% for fH = 15 625Hz]
The capture range is large enough to compensate for possible variations. - Synchronizationrange of the vertical oscillator is quite large which consequentlyallows use of less accurate components :
[R = 910 k, 5 % and C = 180 nF, 5 %]
- Since the frame flyback time is short enough at supply voltage used here, the flyback generator is not used in this application.
Video Input 100nF
1.5k 1M
TEA2037A
1F
470 1W 2.2F Line Darlington
2037A-35.EPS
V CC1
47 1N4148
2.2k
11/17
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
III.1.2 - Monitor with Geometry and Frequency Adjustments (see Figure 29) CHARACTERISTICS - Screen : 12" Colour - Capture range : = 5s - Frame deflection yoke : 18mH, 10, - Holding range : 10s 500mA peak-to-peak - Input signal : negative TTL sync (line + frame) - VCC = + 12V with flyback generator - Dissipated power : 0.9W - Frame flyback time : 0.7ms - Adjustments : - Vertical frequency : 50/60Hz * Vertical amplitude - Vertical free-running period : 23ms * Vertical linearity (adjustable) * Vertical frequency - Horizontal frequency : 15.7kHz * Horizontal frequency (adjustable) * Horizontal phase-shift Figure 29
150
100F P1 : Vertical Amplitude P2 : Vertical Linearity P3 : Vertical Frequency P4 : Horizontal Frequency P5 : Horizontal Shift 1-2-3 switching : Vertical Position
100nF 1N4148
VCC
+12V
VCC1
1N4002 P3 470k 470k
180nF
47F
1
16
2
7
3
2.2
10k
TTL Sync
22nF
Line Flyback 11 15 8
Frame Yoke 18mH, 10 18k 680pF 100k 470nF P2 180k 1000F
6
47nF
15k
330 1 2 3 1.2k 330
TEA2037A
V CC1
10
9
4
5
12
13 14
47k
22nF
22nF
VCC
3.9k
P5
22k
P1 180 1/2W 2.2F Line Darlington 47 10
1F
22k
P4
100
100k
100k 39k
220
VCC
VCC1
1N4148
12/17
2037A-36.EPS
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
III.1.3 - High Frequency Monitor (see Figure 30) CHARACTERISTICS - Screen : 14" Colour - Frame deflection yoke : 11mH, 7, 750mA peak-to-peak - VCC = + 14 V with flyback generator - Frame flyback time : 0.6ms - Vertical frequency : 72Hz - Vertical free-running period : 16ms (adjustable) - Horizontal frequency : 35kHz (adjustable) - Line flyback time : 5.5s Figure 30
2.2
VC C
- Capture range : 5s (@sync pulse = 4.7s) - Input signal : negative TTL sync (line + frame) - Dissipated power : 1.4W (heatsink required) - Adjustments : * Vertical amplitude * Vertical linearity * Vertical frequency * Horizontal frequency
170 100F
VCC1
P3
1000F
1N4002
P1 : Vertical Amplitude P2 : Vertical Linearity P3 : Vertical Frequency
+14V
470k 470k
P4 : Horizontal Frequency
100nF 1N4148
150nF
47F
1
16
2
7
3 8
Frame Yoke 18mH, 10
2.2 47k 330nF
P2
10k
TTL Sync 22nF Line Flyback
15
TEA2037A
680pF
11 6
39k
68k
47nF
15k
2200F
10
9
4
5
12 13
14 VCC
4.7k 6.8nF 1nF 3.9k 22k
100
P1
1F
22k
P4
220 1/2W 2.2F
Line Darlington
10
1
18k
180
47
VCC1 1N4148
13/17
2037A-37.EPS
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
III.2 - Black & White TV Application (see Figure 31) CHARACTERISTICS - Screen : 20" B & W 110o - Frame yoke : 30mH, 12, 850mApeak-to-peak - VCC = + 24 V with flyback generator - Frame flyback time : 1ms - Vertical frequency : 50Hz - Vertical free-running period : 24.5ms - Horizontal frequency : 15 625Hz (adjustable) - Capture range : 2 s Figure 31
4.7 P1 : Vertical Amplitude P2 : Vertical Linearity 24V 2.2k Frame Blanking P3 : Horizontal Frequency
- Holding range : 4.5 s - Input signal : composite video - Dissipated power : 2.3W o (10 C/W - heatsink required) - Adjustments : * Vertical amplitude * Vertical linearity * Horizontal frequency
VC C
1k
100F
VCC1
470F 910k 5%
+24V
1N4002
Video Input
1.5k
220pF
100nF
180nF 5%
1M
1
16
2
7
3
2.2
47F
1N4148
100nF
15
8
Frame Yoke 30mH, 12 100k 220k 33k P2
47 0F
Line Flyback
15k
22nF
11
TEA2037A
6
47nF
680nF
10 9
4
5
12 1 3 14
100k 4.7k
4.7nF
680pF 15k
680nF 15k
47k
22nF
V CC
P1 100
1
2.2F
4.7k
10
P3
470 1W 2.2F
Line Darlington
2037A-38.EPS
47
V CC1
1N4148
14/17
680
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
III.3 - Using Composite TTL Synchronization Since the threshold level on input Pin 15 is internally set at 1.6V, the device can directly accept TTL signals. However, a series resistor is required to limit the current sunk by the on-chip transistor (Pin 15). Figure 32 III.4 - Direct Frame Synchronization The vertical scanning can be directly synchronized by the frame oscillator (Pin 1) and without any need of using the synchronization input (Pin 15). Figure 35 illustrates an example : In this case, only the line sync pulse is applied to Pin 15. Figure 35
VCC1 16 680k
Reference
10k
2037A-39.EPS
TEA2037A
1 15 10k
15 10k
If composite sync signal is not available, line and frame sync signals can be recombined at circuit input as illustrated in Figure 33. Figure 33
Line Sync Input 10k
2037A-40.EPS
Negative Line Sync
15
TEA2037A
Frame Sync Input
Figure 34 : Application Example
Line Sync Input 10k 15
III.5 - Constant Amplitude 50/60Hz Switching In applications requiring 50/60Hz standard switching feature, the arrangement shown below allows to maintain the amplitude of the oscillator saw-tooth (Pin 1) constant thus yielding uniform vertical scanning. Figure 36
VCC1 60Hz Amplitude Adjust 60Hz 50Hz
TEA2037A
330
Frame Sync Input
33nF
47k
TEA2037A
Vertical Oscillator
2037A-43.EPS
1
2037A-41.EPS
Note : Specified component values are purely theoretical and must be calculated to meet specific application requirements.
Figure 37
PIN 11 VOLTAGE(V) Upper Threshold 3.1 Hz 60 Hz 50 2 60Hz Sync 50Hz Sync Lower Threshold
This arrangement is particularly interesting in applications where the available signals differ from those commonly used. An example is the case where the frame signal is of quite long duration (sometimes as long as frame blanking period). In such case, efficient synchronization can be achieved by differentiating the signal so that it will behave as a signal of only few lines duration which is the condition required for appropriate frame and line sync separation and also a picture without flag effect.
Constant Amplitude
2037A-44.EPS
t
15/17
2037A-42.EPS
Positive Frame Sync
220nF
TEA2037A
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
A practical application configuration is illustrated in Figure 38. Figure 38
V CC1 2.2k
scanning at a reduced supply voltage (e.g. +6V) and then supply the overall configuration by the power available on the line transformer (see Figure 41). Figure 39
VCC1 16 R1
910k
10k
16 1
TEA2037A
VCC
10k
50Hz Amplitude Adjust T
150nF
TEA2037A
R2
9
14
2037A-45.EPS
C
2037A-46.EPS
50Hz : T conduc ts 60Hz : T turnedoff
R3
PIN 9 VOLTAGE (V)
III.6 - Modifying the Line Output Duration (see Figures 39 and 40) The line output pulse duration is determined by two internally set threshold levels. This interval can be altered by modifying the charge current of the line oscillator (Pin 9). III.7 - Starting the TEA2037A from a +6V Power Supply The line oscillator of TEA2037Ais capable of starting at a low supply voltage (< 6V). The period of oscillation is practically the same as at nominal operation. It is thus possible to initiate the line Figure 16
Figure 40
6.6 4.8 3.2 t
PIN 14 VOLTAGE (V)
t
+25V +6V ... +12V POWER SUPPLY 100F 1k
EHT TRANSFORMER EHT
V CC1 16 7
VCC2
14
TEA2037A
LINE YOKE
16/17
2037A-48.EPS
2037A-47.EPS
TEA2037A - HORIZONTAL & VERTICAL DEFLECTION CIRCUIT
IV - DESIGN CONSIDERATIONS IV.1 - Precautions for Interlaced Scanning - The links interconnecting the ground terminals of VCC and VCC1 power supplies, as well as those of device decoupling capacitors, must be kept to as short as possible - Ahigh value decouplingcapacitor can be used for VCC supply, provided that a good quality low series resistance capacitor is employed. Interlacing is very sensitive to decoupling quality. The value of the decoupling capacitor can vary from 22F to 100F. - The interconnecting links between the frame oscillator capacitor, the line oscillator capacitor and TEA2037A grounds must be kept to as short as possible. Perfect line and frame synchronization is achieved by observing the above guidelines and recommendations. IV.2 - Printed Circuit Board Layout The usual precautions observed in design of TV timebase pc boards must be employed The line output stage handles high amounts of voltage and current. Components employed must therefore be appropriately rated, the width of and the clearance between the wiring tracks should be carefully selected. All connectionsmust be as short as possible and all signals at the line frequency gathered at this section. The supply to the frame scanning section of the circuit must not be influenced by the horizontal scanning function, particularly when interlaced scanning is used. Generally speaking, interactions on the pc board between the high-gain/low-level and the high-current sections of the output stages must be minimized by as much as possible. As indicated in previous chapters, the four center pins of the device must be earthed. The pad used for this purpose must be as large as possible since it acts as the heatsink for the device. A cruciform pad underlying the circuit should be employed. There should be a single connection to the chassis earth terminal.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
17/17

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